Peter Jamieson, Ph.D.
Education
- Ph.D., Computer Engineering, University of Toronto
- M.S., Computer Engineering, University of Toronto
- B.S., Computer Engineering, University of Ottawa
Research Interests
- Mobile Computing with FPGAs
- Genetic Algorithms for Placement
- Placement Improvement
- Verilog Synthesis
- Serious Games
- Education
Research Bio
Dr. Peter Jamieson completed his doctorate and masters studies at the University of Toronto and his bachelor’s degree at the University of Ottawa, all in the field of Computer Engineering.
Before joining 黑料社区’s department of Electrical and Computer Engineering, he was a research associate at Imperial College in London, U.K in a partnership with Nokia.
Throughout these positions, Dr. Jamieson researched an array of topics including parallel systems, Field Programmable Gate Array (FPGA) architecture and computer aided design (CAD), and low-power mobile computing.
He helped develop an open-source tool called Verilog-to-Routing (VTR) that helps FPGA researchers and industrial partners such as Motorola and Toyota evaluate ideas related to FPGAs. Dr. Jamieson is the creator of another open-source tool Odin II, which is a Verilog synthesis tool fundamental to the VTR flow.
In 2009, Dr. Jamieson joined the Electrical and Computer Engineering department and has focuses his research efforts in a number of synergistic directions. First, he continues his contributions in FPGA research, collaborating with other researchers around the world. In 2017-18, he joined researchers at Boston University to look into FPGAs as part of cloud computing. His focus was on how OpenCL can help design hardware for cloud applications, and he implemented a number of agent-based simulation applications in high performance computing (HPC) domain.
Recently, his research focus is on Genetic Algorithms for solving optimization problems, accelerating audio encoders on FPGAs, improving overlay architectures implemented on top of FPGAs, and leveraging AI within each of these domains.
Finally, Dr. Jamieson’s research focuses on engineering education and serious games. He investigates how various technologies as related to computer engineering can impact higher education. For example, he has investigated how Arduino and RaspberryPi boards are used in undergraduate education, and how graph theory can be applied to providing evidence of learning in mind maps. He created a game, called verilogTown, that allows players to solve city traffic flow problems by writing the Verilog hardware control for the traffic lights.
Experience
- Associate Professor, 黑料社区, 2015 –Present
- Assistant Professor, 黑料社区, 2009 –2015
- Visiting Professor, The University of British Columbia, 2012
- Visiting Professor, Simon Fraser University, 2012
Honors and Awards
- 2015 Distinguished Teaching Award
Principle Publications
Book Chapters
- "Gaming with Purpose: Heuristic Understanding of Ubiquitous Game Development and Design for Human Computation" Lindsay Grace and Peter Jamieson. IEEE Handbook of Digital Games (ISBN: 978-1-118-32803-3). Editors M. Angelides and H. Agius. Wiley-IEEE Press - 2014
Journal Articles
- "Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators" Robert Collier, Christian Fobel, Ryan Pattison, Gary Grewal, Shawki Areibi, and Peter Jamieson. Journal of Evolutionary Intelligence. October 2014.
- "Analyzing System-Level Information's Correlation to FPGA Placement" Farnaz Gharibian, Lesley Shannon, Peter Jamieson, and Kevin Chung. ACM Transactions on Reconfigurable Technology and Systems. Vol. 6. Number 3. October 2013.
- "Power consumption benchmarking for reconfigurable platforms". Teemu Pitkanen, Peter Jamieson, Tobias Becker, Sami Moisio, and Jarmo Takala. Analog Integrated Circuits and Signal Processing
- "VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling". Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Mark Fang, and Jonathan Rose, ACM Transactions on Reconfigurable Technology and Systems. Vol. 4. Number 4. December 2011.
- "Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters" Peter Jamieson and Jonathan Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 18. Number 12, pp 1696 -1709, 2010.